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general description the max11612?ax11617 low-power, 12-bit, multi- channel analog-to-digital converters (adcs) feature internal track/hold (t/h), voltage reference, clock, and an i 2 c-compatible 2-wire serial interface. these devices operate from a single supply of 2.7v to 3.6v (max11613/max11615/max11617) or 4.5v to 5.5v (max11612/max11614/max11616) and require only 670? at the maximum sampling rate of 94.4ksps. supply current falls below 230? for sampling rates under 46ksps. autoshutdown powers down the devices between conversions, reducing supply current to less than 1? at low throughput rates. the max11612/max11613 have 4 analog input channels each, the max11614/max11615 have 8 analog input channels each, while the max11616/max11617 have 12 analog input channels each. the fully differential analog inputs are software configurable for unipolar or bipolar, and single-ended or differential operation. the full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from 1v to v dd . the max11613/ max11615/max11617 feature a 2.048v internal refer- ence and the max11612/max11614/max11616 feature a 4.096v internal reference. the max11612/max11613 are available in an 8-pin ?ax package and the max11613 is available in an ultra-small, 1.9mm x 2.2mm, 12-bump wafer-level pack- age (wlp). the max11614?ax11617 are available in a 16-pin qsop package. the max11612?ax11617 are guaranteed over the extended temperature range (-40? to +85?). for pin-compatible 10-bit parts, refer to the max11606?ax11611 data sheet. for pin-compatible 8- bit parts, refer to the max11600?ax11605 data sheet. applications features high-speed i 2 c-compatible serial interface 400khz fast mode 1.7mhz high-speed mode single-supply 2.7v to 3.6v (max11613/max11615/max11617) 4.5v to 5.5v (max11612/max11614/max11616) ultra-small packages 8-pin max (max11612/max11613) 1.9mm x 2.2mm, 12-bump wlp (max11613) 16-pin qsop (max11614Cmax11617) internal reference 2.048v (max11613/max11615/max11617) 4.096v (max11612/max11614/max11616) external reference: 1v to v dd internal clock 4-channel single-ended or 2-channel fully differential (max11612/max11613) 8-channel single-ended or 4-channel fully differential (max11614/max11615) 12-channel single-ended or 6-channel fully differential (max11616/max11617) internal fifo with channel-scan mode low power 670 a at 94.4ksps 230 a at 40ksps 60 a at 10ksps 6 a at 1ksps 0.5 a in power-down mode software-configurable unipolar/bipolar max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages ________________________________________________________________ maxim integrated products 1 ordering information 19-4561; rev 3; 2/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin- package i 2 c slave address max11612 eua+ -40? to +85? 8 ?ax 0110100 max11613 eua+ -40? to +85? 8 ?ax 0110100 max11613 ewc+* -40? to +85? 12 wlp 0110100 max11614 eee+ -40? to +85? 16 qsop 0110011 max11615 eee+ -40? to +85? 16 qsop 0110011 max11616 eee+ -40? to +85? 16 qsop 0110101 max11617 eee+ -40? to +85? 16 qsop 0110101 pin configurations, typical operating circuit, and selector guide appear at end of data sheet. autoshutdown is a trademark of maxim integrated products, inc. ?ax is a registered trademark of maxim integrated products, inc. + denotes a lead(pb)-free/rohs-compliant package. * future product?ontact factory for availability. handheld portable applications medical instruments battery-powered test equipment solar-powered remote systems received-signal-strength indicators system supervision
max11612?ax11617 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial, 12-bit adcs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 2.7v to 3.6v (max11613/max11615/max11617), v dd = 4.5v to 5.5v (max11612/max11614/max11616), v ref = 2.048v (max11613/max11615/max11617), v ref = 4.096v (max11612/max11614/max11616), f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?, see tables 1? for programming notation.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v ain0?in11, ref to gnd ............-0.3v to the lower of (v dd + 0.3v) and 6v sda, scl to gnd.....................................................-0.3v to +6v maximum current into any pin .........................................?0ma continuous power dissipation (t a = +70?) 8-pin ?ax (derate 5.9mw/? above +70?) ..........470.6mw 16-pin qsop (derate 8.3mw/? above +70?)........666.7mw 12-pin wlp (derate 16.1mw/? above +70?) .........1288mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units dc accuracy (note 2) resolution 12 bits relative accuracy inl (note 3) ? lsb differential nonlinearity dnl no missing codes over temperature ? lsb offset error ? lsb offset-error temperature coefficient relative to fsr 0.3 ppm/ c gain error (note 4) ? lsb gain-temperature coefficient relative to fsr 0.3 ppm/ c channel-to-channel offset matching ?.1 lsb channel-to-channel gain matching ?.1 lsb dynamic performance (f in(sine-wave) = 10khz, v in(p-p) = v ref , f sample = 94.4ksps) signal-to-noise plus distortion sinad 70 db total harmonic distortion thd up to the 5th harmonic -78 db spurious-free dynamic range sfdr 78 db full-power bandwidth sinad > 68db 3 mhz full-linear bandwidth -3db point 5 mhz conversion rate internal clock 7.5 conversion time (note 5) t conv external clock 10.6 ?
max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 2.7v to 3.6v (max11613/max11615/max11617), v dd = 4.5v to 5.5v (max11612/max11614/max11616), v ref = 2.048v (max11613/max11615/max11617), v ref = 4.096v (max11612/max11614/max11616), f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?, see tables 1? for programming notation.) (note 1) parameter symbol conditions min typ max units internal clock, scan[1:0] = 01 51 internal clock, scan[1:0] = 00 cs[3:0] = 1011 (max11616/max11617) 51 throughput rate f sample external clock 94.4 ksps track/hold acquisition time 800 ns internal clock frequency 2.8 mhz external clock, fast mode 60 aperture delay (note 6) t ad external clock, high-speed mode 30 ns analog input (ain0Cain11) unipolar 0 v ref input-voltage range, single- ended and differential (note 7) bipolar 0 v ref /2 v input multiplexer leakage current on/off leakage current, v ain _ = 0 or v dd 0.01 1a input capacitance c in 22 pf internal reference (note 8) m ax11613/m ax 11615/max 11617 1.968 2.048 2.128 reference voltage v ref t a = +25? m ax11612/m ax 11614/max 11616 3.936 4.096 4.256 v reference-voltage temperature coefficient tcv ref 25 ppm/ c ref short-circuit current 2ma ref source impedance 1.5 k ? external reference ref input-voltage range v ref (note 9) 1 v dd v ref input current i ref f sample = 94.4ksps 40 ? digital inputs/outputs (scl, sda) input-high voltage v ih 0.7 x v dd v input-low voltage v il 0.3 x v dd v input hysteresis v hyst 0.1 x v dd v input current i in v in = 0 to v dd 10 ? input capacitance c in 15 pf output low voltage v ol i sink = 3ma 0.4 v
max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 2.7v to 3.6v (max11613/max11615/max11617), v dd = 4.5v to 5.5v (max11612/max11614/max11616), v ref = 2.048v (max11613/max11615/max11617), v ref = 4.096v (max11612/max11614/max11616), f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?, see tables 1? for programming notation.) (note 1) parameter symbol conditions min typ max units power requirements max11613/max11615/max11617 2.7 3.6 supply voltage v dd max11612/max11614/max11616 4.5 5.5 v internal reference 900 1150 f sample = 94.4ksps external clock external reference 670 900 internal reference 530 f sample = 40ksps internal clock external reference 230 internal reference 380 f sample = 10ksps internal clock external reference 60 internal reference 330 f sample =1ksps internal clock external reference 6 supply current i dd shutdown (internal ref off) 0.5 10 ? power-supply rejection ratio psrr full-scale input (note 10) 0.5 2.0 lsb/v timing characteristics (figure 1) (v dd = 2.7v to 3.6v (max11613/max11615/max11617), v dd = 4.5v to 5.5v (max11612/max11614/max11616), v ref = 2.048v (max11613/max11615/max11617), v ref = 4.096v (max11612/max11614/max11616), f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?, see tables 1? for programming notation.) (note 1) parameter symbol conditions min typ max units timing characteristics for fast mode serial-clock frequency f scl 400 khz bus free time between a stop (p) and a start (s) condition t buf 1.3 ? hold time for start (s) condition t hd , sta 0.6 ? low period of the scl clock t low 1.3 ? high period of the scl clock t high 0.6 ? setup time for a repeated start condition (sr) t su , sta 0.6 ? data hold time (note 11) t hd , dat 0 900 ns data setup time t su , dat 100 ns rise time of both sda and scl signals, receiving t r measured from 0.3v dd - 0.7v dd 20 + 0.1c b 300 ns fall time of sda transmitting t f measured from 0.3v dd - 0.7v dd (note 12) 20 + 0.1c b 300 ns setup time for stop (p) condition t su , sto 0.6 ? capacitive load for each bus line c b 400 pf pulse width of spike suppressed t sp 50 ns
max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units timing characteristics for high-speed mode (c b = 400pf, note 13) serial-clock frequency f sclh (note 14) 1.7 mhz hold time, repeated start condition (sr) t hd , sta 160 ns low period of the scl clock t low 320 ns high period of the scl clock t high 120 ns setup time for a repeated start condition (sr) t su , sta 160 ns data hold time t hd , dat (note 11) 0 150 ns data setup time t su , dat 10 ns rise time of scl signal (current source enabled) t rcl 20 80 ns rise time of scl signal after acknowledge bit t rcl1 measured from 0.3v dd - 0.7v dd 20 160 ns fall time of scl signal t fcl measured from 0.3v dd - 0.7v dd 20 80 ns rise time of sda signal t rda measured from 0.3v dd - 0.7v dd 20 160 ns fall time of sda signal t fda measured from 0.3v dd - 0.7v dd (note 12) 20 160 ns setup time for stop (p) condition t su , sto 160 ns capacitive load for each bus line c b 400 pf pulse width of spike suppressed t sp (notes 11 and 14) 0 10 ns timing characteristics (figure 1) (continued) (v dd = 2.7v to 3.6v (max11613/max11615/max11617), v dd = 4.5v to 5.5v (max11612/max11614/max11616), v ref = 2.048v (max11613/max11615/max11617), v ref = 4.096v (max11612/max11614/max11616), f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?, see tables 1? for programming notation.) (note 1) note 1: all wlp devices are 100% production tested at t a = +25?. specifications over temperature limits are guaranteed by design and characterization. note 2: for dc accuracy, the max11612/max11614/max11616 are tested at v dd = 5v and the max11613/max11615/max11617are tested at v dd = 3v. all devices are configured for unipolar, single-ended inputs. note 3: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offsets have been calibrated. note 4: offset nulled. note 5: conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. conversion time does not include acquisition time. scl is the conversion clock in the external clock mode. note 6: a filter on the sda and scl inputs suppresses noise spikes and delays the sampling instant. note 7: the absolute input-voltage range for the analog inputs (ain0?in11) is from gnd to v dd . note 8: when the internal reference is configured to be available at ain_/ref (sel[2:1] = 11), decouple ain_/ref to gnd with a 0.1? capacitor and a 2k ? series resistor (see the typical operating circuit ). note 9: adc performance is limited by the converter? noise floor, typically 300? p-p . note 10: measured as for the max11613/max11615/max11617:
max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages 6 _______________________________________________________________________________________ typical operating characteristics (v dd = 3.3v (max11613/max11615/max11617), v dd = 5v (max11612/max11614/max11616), f scl = 1.7mhz, (50% duty cycle), f sample = 94.4ksps, single-ended, unipolar, t a = +25?, unless otherwise noted.) -0.5 -0.2 -0.4 -0.3 0.2 0.1 0.1 0 0.3 0.5 0 4000 differential nonlinearity vs. digital code max11612 toc01 digital output code dnl (lsb) 1000 1500 500 2000 2500 3000 3500 0.4 -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 integral nonlinearity vs. digital code max11612 toc02 digital output code inl (lsb) 04000 1000 1500 500 2000 2500 3000 3500 -180 -160 -140 -120 -100 -80 -60 0 10k 20k 30k 40k 50k fft plot max11612 toc03 frequency (hz) amplitude (dbc) f sample = 94.4ksps f in = 10khz 300 400 350 500 450 600 550 650 750 700 800 -40 -10 5 -25 20 35 50 65 80 supply current vs. temperature max11612 toc04 temperature ( c) supply current ( a) internal reference max11617/max11615/ max11613 internal reference max11616/max11614/ max11612 external reference max11616/max11614/ max11612 external reference max11617/max11615/ max11613 setup byte ext ref: 10111011 int ref: 11011011 0 0.2 0.1 0.4 0.3 0.5 0.6 2.7 5.2 shutdown supply current vs. supply voltage max11612 toc05 supply voltage (v) i dd ( a) 3.7 3.2 4.2 4.7 sda = scl = v dd 0 0.10 0.05 0.20 0.15 0.30 0.25 0.35 0.45 0.40 0.50 -40 -10 5 -25 20 35 50 65 80 shutdown supply current vs. temperature max11612 toc06 temperature ( c) supply current ( a) max11616/max11614/max11612 max11617/max11615/max11613 and for the max11612/max11614/max11616, where n is the number of bits: note 11: a master device must provide a data hold time for sda (referred to v il of scl) to bridge the undefined region of scl? falling edge (see figure 1). note 12: the minimum value is specified at t a = +25?. note 13: c b = total capacitance of one bus line in pf. note 14: f scl must meet the minimum clock low time plus the rise/fall times. vvvv v vv fs fs ref n (. ) (. ) (. . ) 55 45 21 55 45 ? ? ? [] ? ? ? ? ? ? ? ? timing characteristics (figure 1) (continued) (v dd = 2.7v to 3.6v (max11613/max11615/max11617), v dd = 4.5v to 5.5v (max11612/max11614/max11616), v ref = 2.048v (max11613/max11615/max11617), v ref = 4.096v (max11612/max11614/max11616), f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?, see tables 1? for programming notation.) (note 1)
max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages _______________________________________________________________________________________ 7 200 300 250 350 400 450 500 550 600 650 700 750 800 0 20 30 40 60 80 100 average supply current vs. conversion rate (external clock) max11612 toc07 conversion rate (ksps) average i dd ( a) 010 50 70 90 a b a) internal reference always on b) external reference max11616/max11614/max11612 average supply current vs. conversion rate (external clock) max11612 toc08 conversion rate (ksps) average i dd ( a) 80 60 40 20 300 400 500 600 700 800 200 0100 max11617/max11615/max11613 a) internal reference always on b) external reference a b 0.9990 0.9994 0.9992 0.9998 0.9996 1.0002 1.0000 1.0004 1.0008 1.0006 1.0010 -40 -10 5 -25 20 35 50 65 80 internal reference voltage vs. temperature max11612 toc09 temperature ( c) v ref normalized normalized to value at t a = +25 c max11616/max11614/max11612 max11617/max11615/max11613 0.99990 0.99994 0.99992 0.99998 0.99996 1.00002 1.00000 1.00004 1.00008 1.00006 1.00010 2.7 3.3 3.6 3.9 3.0 4.2 4.5 4.8 5.1 5.4 normalized reference voltage vs. supply voltage max11612 toc10 v dd (v) v ref (v) max11616/max11614/max11612 normalized to reference value at v dd = 5v max11617/max11615/max11613 normalized to reference value at v dd = 3.3v offset error vs. temperature max11612 toc11 temperature ( c) offset error (lsb) 80 65 35 50 -10 5 20 -25 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 -1.0 -40 offset error vs. supply voltage max11612 toc12 v dd (v) offset error (lsb) 5.2 5.5 4.7 4.2 3.7 3.2 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 -2.0 2.7 typical operating characteristics (continued) (v dd = 3.3v (max11613/max11615/max11617), v dd = 5v (max11612/max11614/max11616), f scl = 1.7mhz, (50% duty cycle), f sample = 94.4ksps, single-ended, unipolar, t a = +25?, unless otherwise noted.) gain error vs. temperature max11612 toc13 temperature ( c) gain error (lsb) 80 65 35 50 -10 5 20 -25 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 -40 gain error vs. supply voltage max11612 toc14 v dd (v) gain error (lsb) 5.2 5.5 4.7 4.2 3.7 3.2 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 -2.0 2.7
max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages 8 _______________________________________________________________________________________ pin description pin max11612 max11613 ?ax wlp max11614 max11615 max11616 max11617 name function 1, 2, 3 a1, a2, a3 5, 6, 7 5, 6, 7 ain0, ain1, ain2 8?2 8?2 ain3?in7 4, 3, 2 ain8?in10 analog inputs 4 a4 ain3/ref analog input 3/reference input or output. selected in the setup register (see tables 1 and 6). 1 ref reference input or output. selected in the setup register (see tables 1 and 6). 1 ain11/ref analog input 11/reference input or output. selected in the setup register (see tables 1 and 6). 5 c4 13 13 scl clock input 6 c3 14 14 sda data input/output 7 b1, b2, b3, b4, c2 15 15 gnd ground 8c11616 v dd positive supply. bypass to gnd with a 0.1? capacitor. 2, 3, 4 n.c. no connection. not internally connected. t hd.sta t su.dat t high t r t f t hd.dat t hd.sta s sr a scl sda t su.sta t low t buf t su.sto ps t hd.sta t su.dat t high t fcl t hd.dat t hd.sta s sr a scl sda t su.sta t low t buf t su.sto s t rcl t rcl1 hs mode f/s mode a. f/s-mode 2-wire serial-interface timing b. hs-mode 2-wire serial-interface timing t fda t rda t t r t f p figure 1. 2-wire serial-interface timing
detailed description the max11612?ax11617 analog-to-digital converters (adcs) use successive-approximation conversion tech- niques and fully differential input track/hold (t/h) cir- cuitry to capture and convert an analog signal to a serial 12-bit digital output. the max11612/max11613 are 4-channel adcs, the max11614/max11615 are 8-channel adcs, and the max11616/max11617 are 12-channel adcs. these devices feature a high-speed, 2-wire serial interface supporting data rates up to 1.7mhz. figure 2 shows the simplified internal structure for the max11616/max11617. power supply the max11612?ax11617 operate from a single sup- ply and consume 670? (typ) at sampling rates up to 94.4ksps. the max11613/max11615/max11617 fea- ture a 2.048v internal reference and the max11612/ max11614/max11616 feature a 4.096v internal refer- ence. all devices can be configured for use with an external reference from 1v to v dd . analog input and track/hold the max11612?ax11617 analog-input architecture contains an analog-input multiplexer (mux), a fully dif- ferential track-and-hold (t/h) capacitor, t/h switches, a comparator, and a fully differential switched capacitive digital-to-analog converter (dac) (figure 4). in single-ended mode, the analog input multiplexer con- nects c t/h between the analog input selected by cs[3:0] (see the configuration/setup bytes (write cycle) section) and gnd (table 3). in differential mode, the analog-input multiplexer connects c t/h to the + and - analog inputs selected by cs[3:0] (table 4). max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages _______________________________________________________________________________________ 9 analog input mux ain1 ain11/ref ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain0 scl sda input shift register setup register configuration register control logic reference 4.096v (max11616) 2.048v (max11617) internal oscillator output shift register and ram ref t/h 12-bit adc v dd gnd max11616 max11617 figure 2. max11616/max11617 simplified functional diagram v dd i ol i oh v out 400pf sda figure 3. load circuit
max11612?ax11617 during the acquisition interval, the t/h switches are in the track position and c t/h charges to the analog input signal. at the end of the acquisition interval, the t/h switches move to the hold position retaining the charge on c t/h as a stable sample of the input signal. during the conversion interval, the switched capacitive dac adjusts to restore the comparator input voltage to 0v within the limits of a 12-bit resolution. this action requires 12 conversion clock cycles and is equivalent to transferring a charge of 11pf (v in+ - v in- ) from c t/h to the binary weighted capacitive dac, forming a digital representation of the analog input signal. sufficiently low source impedance is required to ensure an accurate sample. a source impedance of up to 1.5k ? does not significantly degrade sampling accuracy. to minimize sampling errors with higher source impedances, connect a 100pf capacitor from the analog input to gnd. this input capacitor forms an rc filter with the source impedance limiting the analog-input bandwidth. for larg- er source impedances, use a buffer amplifier to maintain analog-input signal integrity and bandwidth. when operating in internal clock mode, the t/h circuitry enters its tracking mode on the eighth rising clock edge of the address byte, see the slave address section. the t/h circuitry enters hold mode on the falling clock edge of the acknowledge bit of the address byte (the ninth clock pulse). a conversion or a series of conversions is then internally clocked and the max11612?ax11617 holds scl low. with external clock mode, the t/h circuitry enters track mode after a valid address on the rising edge of the clock during the read (r/ w = 1) bit. hold mode is then entered on the rising edge of the second clock pulse during the shifting out of the first byte of the result. the conversion is performed during the next 12 clock cycles. the time required for the t/h circuitry to acquire an input signal is a function of the input sample capaci- tance. if the analog-input source impedance is high, the acquisition time constant lengthens and more time must be allowed between conversions. the acquisition time (t acq ) is the minimum time needed for the signal to be acquired. it is calculated by: t acq 9 (r source + r in ) c in where r source is the analog-input source impedance, r in = 2.5k ? , and c in = 22pf. t acq is 1.5/f scl for internal clock mode and t acq = 2/f scl for external clock mode. analog input bandwidth the max11612?ax11617 feature input-tracking circuit- ry with a 5mhz small-signal bandwidth. the 5mhz input bandwidth makes it possible to digitize high-speed tran- sient events and measure periodic signals with band- widths exceeding the adc? sampling rate by using under sampling techniques. to avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. analog input range and protection internal protection diodes clamp the analog input to v dd and gnd. these diodes allow the analog inputs to low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages 10 ______________________________________________________________________________________ track track hold c t/h c t/h track track hold ain0 ain1 ain2 ain3/ref gnd analog input mux capacitive dac ref capacitive dac ref max11612 max11613 hold hold track hold v dd /2 figure 4. equivalent input circuit
max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages ______________________________________________________________________________________ 11 swing from (gnd - 0.3v) to (v dd + 0.3v) without caus- ing damage to the device. for accurate conversions, the inputs must not go more than 50mv below gnd or above v dd . single-ended/differential input the sgl/ dif of the configuration byte configures the max11612?ax11617 analog-input circuitry for single- ended or differential inputs (table 2). in single-ended mode (sgl/ dif = 1), the digital conversion results are the difference between the analog input selected by cs[3:0] and gnd (table 3). in differential mode (sgl/ dif = 0), the digital conversion results are the differ- ence between the + and the - analog inputs selected by cs[3:0] (table 4). unipolar/bipolar when operating in differential mode, the bip/ uni bit of the set-up byte (table 1) selects unipolar or bipolar operation. unipolar mode sets the differential input range from 0 to v ref . a negative differential analog input in unipolar mode causes the digital output code to be zero. selecting bipolar mode sets the differential input range to ? ref /2. the digital output code is bina- ry in unipolar mode and two? complement in bipolar mode. see the transfer functions section. in single-ended mode, the max11612?ax11617 al- ways operates in unipolar mode irrespective of bip/ uni . the analog inputs are internally referenced to gnd with a full-scale input range from 0 to v ref . 2-wire digital interface the max11612?ax11617 feature a 2-wire interface consisting of a serial-data line (sda) and serial-clock line (scl). sda and scl facilitate bidirectional communica- tion between the max11612?ax11617 and the master at rates up to 1.7mhz. the max11612?ax11617 are slaves that transfer and receive data. the master (typi- cally a microcontroller) initiates data transfer on the bus and generates the scl signal to permit that transfer. sda and scl must be pulled high. this is typically done with pullup resistors (750 ? or greater) (see the typical operating circuit ). series resistors (r s ) are optional. they protect the input architecture of the max11612 max11617 from high voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. bit transfer one data bit is transferred during each scl clock cycle. a minimum of 18 clock cycles are required to transfer the data in or out of the max11612?ax11617. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is stable are considered control signals (see the start and stop conditions section). both sda and scl remain high when the bus is not busy. start and stop conditions the master initiates a transmission with a start condi- tion (s), a high-to-low transition on sda while scl is high. the master terminates a transmission with a stop condition (p), a low-to-high transition on sda while scl is high (figure 5). a repeated start condi- tion (sr) can be used in place of a stop condition to leave the bus active and the interface mode unchanged (see the hs mode section). acknowledge bits data transfers are acknowledged with an acknowledge bit (a) or a not-acknowledge bit ( a ). both the master and the max11612?ax11617 (slave) generate acknowledge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (figure 6). to generate a not-acknowledge, the receiver allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves sda high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuc- cessful data transfer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. scl sda sp sr figure 5. start and stop conditions scl sda s not acknowledge acknowledge 12 89 figure 6. acknowledge bits
max11612?ax11617 slave address a bus master initiates communication with a slave device by issuing a start condition followed by a slave address. when idle, the max11612?ax11617 continu- ously wait for a start condition followed by their slave address. when the max11612?ax11617 recognize their slave address, they are ready to accept or send data. see the ordering information for the factory pro- grammed slave address of the selected device. the least significant bit (lsb) of the address byte (r/ w ) determines whether the master is writing to or reading from the max11612?ax11617 (r/ w = 0 selects a write condition, r/ w = 1 selects a read condition). after receiving the address, the max11612?ax11617 (slave) issues an acknowledge by pulling sda low for one clock cycle. bus timing at power-up, the max11612?ax11617 bus timing is set for fast-mode (f/s mode), which allows conversion rates up to 22.2ksps. the max11612?ax11617 must operate in high-speed mode (hs mode) to achieve con- version rates up to 94.4ksps. figure 1 shows the bus tim- ing for the max11612?ax11617? 2-wire interface. hs mode at power-up, the max11612?ax11617 bus timing is set for f/s mode. the bus master selects hs mode by addressing all devices on the bus with the hs-mode master code 0000 1xxx (x = don? care). after success- fully receiving the hs-mode master code, the max11612?ax11617 issue a not-acknowledge, allow- ing sda to be pulled high for one clock cycle (figure 8). after the not-acknowledge, the max11612?ax11617 are in hs mode. the bus master must then send a repeated start followed by a slave address to initiate hs mode communication. if the master generates a stop condition, the max11612?ax11617 return to f/s mode. low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages 12 ______________________________________________________________________________________ 01 1 1 0 0 0 r/w a slave address s scl sda 123456789 max11612/max11613 see ordering information for slave address options and details. figure 7. max11612/max11613 slave address byte 000 1 0xxx a hs-mode master code scl sda s sr f/s mode hs mode figure 8. f/s-mode to hs-mode transfer
configuration/setup bytes (write cycle) a write cycle begins with the bus master issuing a start condition followed by seven address bits (figure 7) and a write bit (r/ w = 0). if the address byte is suc- cessfully received, the max11612?ax11617 (slave) issues an acknowledge. the master then writes to the slave. the slave recognizes the received byte as the set-up byte (table 1) if the most significant bit (msb) is 1. if the msb is 0, the slave recognizes that byte as the configuration byte (table 2). the master can write either one or two bytes to the slave in any order (setup byte, then configuration byte; configuration byte, then setup byte; setup byte or configuration byte only; figure 9). if the slave receives a byte successfully, it issues an acknowledge. the master ends the write cycle by issu- ing a stop condition or a repeated start condition. when operating in hs mode, a stop condition returns the bus into f/s mode (see the hs mode section). max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages ______________________________________________________________________________________ 13 b. two-byte write cycle slave to master master to slave s 1 slave address a 711 w setup or configuration byte setup or configuration byte 8 p or sr 1 a 1 msb determines whether setup or configuration byte s 1 slave address a 711 w setup or configuration byte 8 p or sr 1 a 1 msb determines whether setup or configuration byte a 1 8 a. one-byte write cycle number of bits number of bits figure 9. write cycle bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) reg sel2 sel1 sel0 clk bip/ uni rst x bit name description 7 reg register bit. 1 = setup byte, 0 = configuration byte (table 2). 6 sel2 5 sel1 4 sel0 three bits select the reference voltage and the state of ain_/ref (max11612/max11613/max11616/max11617) or ref (max11614/max11615) (table 6). default to 000 at power-up. 3 clk 1 = external clock, 0 = internal clock. defaults to 0 at power-up. 2 bip/ uni 1 = bipolar, 0 = unipolar. defaults to 0 at power-up (see the unipolar/bipolar section). 1 rst 1 = no action, 0 = resets the configuration register to default. setup register remains unchanged. 0 x don?-care bit. this bit can be set to 1 or 0. table 1. setup byte format
max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages 14 ______________________________________________________________________________________ bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) reg scan1 scan0 cs3 cs2 cs1 cs0 sgl/ dif bit name description 7 reg register bit. 1 = setup byte (see table 1), 0 = configuration byte. 6 scan1 5 scan0 scan select bits. two bits select the scanning configuration (table 5). default to 00 at power-up. 4 cs3 3 cs2 2 cs1 1 cs0 channel select bits. four bits select which analog input channels are to be used for conversion (tables 3 and 4). default to 0000 at power-up. for the max11612/max11613, cs3 and cs2 are internally set to 0. for the max11614/max11615, cs3 is internally set to 0. 0 sgl/ dif 1 = single-ended, 0 = differential (tables 3 and 4). defaults to 1 at power-up. see the single- ended/differential input section. table 2. configuration byte format cs3 1 cs2 1 cs1 cs0 ain0 ain1 ain2 ain3 2 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain11 2 gnd 0000+ - 0001 + - 0010 + - 0011 + - 0100 + - 0101 + - 0110 + - 0111 + - 1000 + - 1001 +- 1010 +- 1011 + - 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved 1 for the max11612/max11613, cs3 and cs2 are internally set to 0. for the max11614/max11615, cs3 is internally set to 0. 2 when sel1 = 1, a single-ended read of ain3/ref (max11612/max11613) or ain11/ref (max11616/max11617) is ignored; scan stops at ain2 or ain10. this does not apply to the max11614/max11615 as each provides separate pins for ain7 and ref. table 3. channel selection in single-ended mode (sgl/ dif = 1)
data byte (read cycle) a read cycle must be initiated to obtain conversion results. read cycles begin with the bus master issuing a start condition followed by seven address bits and a read bit (r/ w = 1). if the address byte is successfully received, the max11612?ax11617 (slave) issues an acknowledge. the master then reads from the slave. the result is transmitted in two bytes; first four bits of the first byte are high, then msb through lsb are con- secutively clocked out. after the master has received the byte(s), it can issue an acknowledge if it wants to continue reading or a not-acknowledge if it no longer wishes to read. if the max11612?ax11617 receive a not-acknowledge, they release sda, allowing the master to generate a stop or a repeated start condition. see the clock modes and scan mode sections for detailed information on how data is obtained and converted. clock modes the clock mode determines the conversion clock and the data acquisition and conversion time. the clock mode also affects the scan mode. the state of the set- up byte? clk bit determines the clock mode (table 1). at power-up, the max11612?ax11617 are defaulted to internal clock mode (clk = 0). internal clock when configured for internal clock mode (clk = 0), the max11612?ax11617 use their internal oscillator as the conversion clock. in internal clock mode, the max11612 max11617 begin tracking the analog input after a valid address on the eighth rising edge of the clock. on the falling edge of the ninth clock, the analog signal is acquired and the conversion begins. while converting the analog input signal, the max11612?ax11617 holds scl low (clock stretching). after the conversion completes, the results are stored in internal memory. if the scan mode is set for multiple conversions, they all happen in succession with each additional result stored in memory. the max11612/ max11613 contain four 12-bit blocks of memory, the max11614/max11615 contain eight 12-bit blocks of memo- ry, and the max11616/max11617 contain twelve 12-bit blocks of memory. once all conversions are complete, the max11612?ax11617 release scl, allowing it to be pulled high. the master can now clock the results out of the mem- ory in the same order the scan conversion has been done at a clock rate of up to 1.7mhz. scl is stretched for a maxi- mum of 8.3? per channel (see figure 10). the device memory contains all of the conversion results when the max11612?ax11617 release scl. max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages ______________________________________________________________________________________ 15 cs3 1 cs2 1 cs1 cs0 ain0 ain1 ain2 ain3 2 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain11 2 0000+ - 0001 -+ 0010 +- 0011 -+ 0100 +- 0101 -+ 0110 +- 0111 -+ 1000 +- 1001 -+ 1010 +- 1011 -+ 1100 reserved 1101 reserved 1110 reserved 1111 reserved 1 for the max11612/max11613, cs3 and cs2 are internally set to 0. for the max11614/max11615, cs3 is internally set to 0. 2 when sel1 = 1, a differential read between ain2 and ain3/ref (max11612/max11613) or ain10 and ain11/ref (max11616/max11617) returns the difference between gnd and ain2 or ain10, respectively. for example, a differential read of 101 1 returns the negative difference between ain10 and gnd. this does not apply to the max11614/max11615 as each provides separate pins for ain7 and ref. in differential scanning, the address increments by 2 until the limit set by cs3?s1 has been reached. table 4. channel selection in differential mode (sgl/ dif = 0)
max11612?ax11617 the converted results are read back in a first-in-first-out (fifo) sequence. if ain_/ref is set to be a reference input or output (sel1 = 1, table 6), ain_/ref is exclud- ed from a multichannel scan. this does not apply to the max11614/max11615 as each provides separate pins for ain7 and ref. the memory contents can be read continuously. if reading continues past the result stored in memory, the pointer wraps around and point to the first result. note that only the current conversion results is read from memory. the device must be addressed with a read command to obtain new conversion results. the internal clock mode? clock stretching quiets the scl bus signal reducing the system noise during conversion. using the internal clock also frees the bus master (typically a microcontroller) from the burden of running the conversion clock, allowing it to perform other tasks that do not need to use the bus. external clock when configured for external clock mode (clk = 1), the max11612?ax11617 use the scl as the conver- sion clock. in external clock mode, the max11612 max11617 begin tracking the analog input on the ninth rising clock edge of a valid slave address byte. two scl clock cycles later, the analog signal is acquired and the conversion begins. unlike internal clock mode, low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages 16 ______________________________________________________________________________________ b. scan mode conversions with internal clock s 1 slave address a 711 r clock stretch number of bits p or sr 1 8 result 8 lsbs 8 result 4 msbs a a 1 a. single conversion with internal clock s 1 slave address 711 r clock stretch a number of bits p or sr 1 8 result 1 ( 4msbs) a 1 a 8 result 1 (8 lsbs) a 8 result n (8lsbs) a 1 8 result n (4msbs) slave to master master to slave clock stretch t acq1 t conv2 t acq2 t convn t acqn t conv t acq 1 1 t conv1 figure 10. internal clock mode read cycles slave address t conv1 t acq1 t acq2 t convn t acqn t conv t acq number of bits number of bits 1 8 a 1 s 1 a 711 r s 1 711 r p or sr 1 8 a 1 a 8 a 8 b. scan mode conversions with external clock 1 1 slave address p or sr result (8 lsbs) 8 a 1 result (4 msbs) a. single conversion with external clock slave to master master to slave result 1 (4 msbs) result 2 (8 lsbs) result n (8 lsbs) a 1 8 result n (4 msbs) a figure 11. external clock mode read cycle
converted data is available immediately after the first four empty high bits. the device continuously converts input channels dictated by the scan mode until given a not acknowledge. there is no need to readdress the device with a read command to obtain new conversion results (see figure 11). the conversion must complete in 1ms, or droop on the track-and-hold capacitor degrades conversion results. use internal clock mode if the scl clock period exceeds 60?. the max11612?ax11617 must operate in external clock mode for conversion rates from 40ksps to 94.4ksps. below 40ksps, internal clock mode is recom- mended due to much smaller power consumption. scan mode scan0 and scan1 of the configuration byte set the scan mode configuration. table 5 shows the scanning configurations. if ain_/ref is set to be a reference input or output (sel1 = 1, table 6), ain_/ref is excluded from a multichannel scan. the scanned results are written to memory in the same order as the conversion. read the results from memory in the order they were converted. each result needs a 2-byte transmission; the first byte begins with four empty bits, during which sda is left high. each byte has to be acknowledged by the master or the memory transmission is terminated. it is not possi- ble to read the memory independently of conversion. applications information power-on reset the configuration and setup registers (tables 1 and 2) default to a single-ended, unipolar, single-channel con- version on ain0 using the internal clock with v dd as the reference and ain_/ref configured as an analog input. the memory contents are unknown after power-up. automatic shutdown automatic shutdown occurs between conversions when the max11612?ax11617 are idle. all analog circuits participate in automatic shutdown except the internal reference due to its prohibitively long wake-up time. when operating in external clock mode, a stop, not- acknowledge, or repeated start condition must be issued to place the devices in idle mode and benefit from automatic shutdown. a stop condition is not nec- essary in internal clock mode to benefit from automatic shutdown because power-down occurs once all con- version results are written to memory (figure 10). when using an external reference or v dd as a reference, all analog circuitry is inactive in shutdown and supply cur- rent is less than 0.5?. the digital conversion results obtained in internal clock mode are maintained in memo- ry during shutdown and are available for access through the serial interface at any time prior to a stop or a repeated start condition. max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages ______________________________________________________________________________________ 17 scan1 scan0 scanning configuration 00 scans up from ain0 to the input selected by cs3?s0. when cs3?s0 exceeds 1011, the scanning stops at ain11. when ain_/ref is set to be a ref input/output, scanning stops at ain2 or ain10. 0 1 *converts the input selected by cs3?s0 eight times (see tables 3 and 4). max11612/max11613: scans upper half of channels. scans up from ain2 to the input selected by cs1 and cs0. when cs1 and cs0 are set for ain0, ain1, and ain2, the only scan that takes place is ain2 (max11612/max11613). when ain/ref is set to be a ref input/output, scanning stops at ain2. max11614/max11615: scans upper quartile of channels. scans up from ain6 to the input selected by cs3?s0. when cs3?s0 is set for ain0?in6, the only scan that takes place is ain6 (max11614/max11615). 10 max11616/max11617: scans upper half of channels. scans up from ain6 to the input selected by cs3?s0. when cs3?s0 is set for ain0?in6, the only scan that takes place is ain6 (max11616/max11617). when ain/ref is set to be a ref input/output, scanning stops at selected channel or ain10. 1 1 *converts channel selected by cs3?s0. * when operating in external clock mode, there is no difference between scan[1:0] = 01 and scan[1:0] = 11, and converting occurs perpetually until not-acknowledge occurs. table 5. scanning configuration
max11612?ax11617 when idle, the max11612?ax11617 continuously wait for a start condition followed by their slave address (see the slave address section). upon reading a valid address byte, the max11612?ax11617 power up. the internal reference requires 10ms to wake up, so when using the internal reference it should be powered up 10ms prior to conversion or powered continuously. wake-up is invisible when using an external reference or v dd as the reference. automatic shutdown results in dramatic power savings, particularly at slow conversion rates and with internal clock. for example, at a conversion rate of 10ksps, the average supply current for the max11613 is 60? (typ) and drops to 6? (typ) at 1ksps. at 0.1ksps the average supply current is just 1?, or a minuscule 3w of power consumption. see average supply current vs. conversion rate in the typical operating characteristics section). reference voltage sel[2:0] of the setup byte (table 1) control the reference and the ain_/ref configuration (table 6). when ain_/ref is configured to be a reference input or reference output (sel1 = 1), differential conversions on ain_/ref appear as if ain_/ref is connected to gnd (see note 2 of table 4). single-ended conversion in scan mode ain_/ref is ignored by the internal limiter, which sets the highest avail- able channel at ain2 or ain10. internal reference the internal reference is 4.096v for the max11612/ max11614/max11616 and 2.048v for the max11613/ max11615/max11617. sel1 of the setup byte controls whether ain_/ref is used for an analog input or a refer- ence (table 6). when ain_/ref is configured to be an internal reference output (sel[2:1] = 11), decouple ain_/ref to gnd with a 0.1? capacitor and a 2k ? series resistor (see the typical operating circuit ). once powered up, the refer ence always remains on until recon- figured. the internal reference requires 10ms to wake up and is accessed using sel0 (table 6). when in shutdown, the internal reference output is in a high-impedance state. the reference should not be used to supply current for external circuitry. the internal reference does not require an external bypass capacitor and works best when left uncon- nected (sel1 = 0). external reference the external reference can range from 1v to v dd . for maximum conversion accuracy, the reference must be able to deliver up to 40? and have an output imped- ance of 500k ? or less. if the reference has a higher out- put impedance or is noisy, bypass it to gnd as close to ain_/ref as possible with a 0.1? capacitor. low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages 18 ______________________________________________________________________________________ sel2 sel1 sel0 reference voltage ain_/ref (max11612/ max11613/ max11616/ max11617) ref (max11614/ max11615) internal reference state 00x v dd analog input not connected always off 0 1 x external reference reference input reference input always off 1 0 0 internal reference analog input not connected always off 1 0 1 internal reference analog input not connected always on 1 1 0 internal reference reference output reference output always off 1 1 1 internal reference reference output reference output always on table 6. reference voltage, ain_/ref, and ref format output code full-scale transition 11 . . . 111 11 . . . 110 11 . . . 101 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 123 0 fs fs - 3/2 lsb fs = v ref zs = gnd input voltage (lsb) max11612 max11617 1 lsb = v ref 4096 figure 12. unipolar transfer function x = don? care.
transfer functions output data coding for the max11612?ax11617 is binary in unipolar mode and two? complement in bipo- lar mode w ith 1 lsb = (v ref /2n) where n is the number of bits (12). code transitions occur halfway between successive-integer lsb values. figures 12 and 13 show the input/output (i/o) transfer functions for unipo- lar and bipolar operations, respectively. layout, grounding, and bypassing only use pc boards. wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. do not run ana- log and digital lines parallel to each other, and do not layout digital signal paths underneath the adc pack- age. use separate analog and digital pcb ground sec- tions with only one star point (figure 14) connecting the two ground systems (analog and digital). for lowest noise operation, ensure the ground return to the star ground? power supply is low impedance and as short as possible. route digital signals far away from sensi- tive analog and reference inputs. high-frequency noise in the power supply (v dd ) could influence the proper operation of the adc? fast com- parator. bypass v dd to the star ground with a network of two parallel capacitors, 0.1? and 4.7?, located as close as possible to the max11612?ax11617 power- supply pin. minimize capacitor lead length for best sup- ply noise rejection, and add an attenuation resistor (5 ? ) in series with the power supply if it is extremely noisy. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the max11612 max11617? inl is measured using the endpoint. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time between the falling edge of the sampling clock and the instant when an actual sample is taken. max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, ______________________________________________________________________________________ 19 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 - fs 0 input voltage (lsb) output code zs = 0 +fs - 1 lsb *v com v ref /2 *v in = (ain+) - (ain-) fs = v ref 2 -fs = -v ref 2 max11612 max11617 1 lsb = v ref 4096 figure 13. bipolar transfer function gnd v logic = 3v/5v 3v or 5v supplies dgnd 3v/5v gnd *optional 4.7 f r* = 5 ? 0.1 f v dd digital circuitry max11612 max11617 figure 14. power-supply grounding connection
low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages 20 ______________________________________________________________________________________ signal-to-noise ratio for a waveform perfectly reconstructed from digital sam- ples, the theoretical maximum snr is the ratio of the full- scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum ana- log-to-digital noise is caused by quantization error only and results directly from the adc? resolution (n bits): snr max[db] = 6.02 db n + 1.76 db in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency? rms amplitude to the rms equivalent of all other adc output signals. effective number of bits effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quanti- zation noise only. with an input range equal to the adc? full-scale range, calculate the enob as follows: enob = (sinad - 1.76)/6.02 total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the input signal? first five harmonics to the fun- damental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order har- monics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next largest distor- tion component. thd vvvv v log = +++ ? ? ? ? ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 sinad db signalrms noiserms thdrms ( ) log = + ? ? ? ? ? ? 20 chip information process: bicmos max11612?ax11617 part input channels internal reference (v) supply voltage (v) inl (lsb) max11612 4 4.096 4.5 to 5.5 1 max11613 4 2.048 2.7 to 3.6 1 max11614 8 4.096 4.5 to 5.5 1 max11615 8 2.048 2.7 to 3.6 1 max11616 12 4.096 4.5 to 5.5 1 max11617 12 2.048 2.7 to 3.6 1 selector guide
max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages ______________________________________________________________________________________ 21 *optional **ain11/ref (max11616/max11617) r s * r s * analog inputs c sda scl gnd v dd sda scl ain0 ain1 rc network* ain3**/ref 3.3v or 5v 5v r p c ref 0.1 f r p 5v max11612 max11617 0.1 f 2k ? typical operating circuit sda scl ain3/ref 1 + + 2 8 7 v dd gnd ain1 ain2 ain0 max top view 3 4 6 5 max11612 max11613 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 (ref) ain11/ref v dd gnd sda scl ain7 ain6 ain5 ain4 ( ) indicates pins on the max11614/max11615. max11614 max11617 qsop (n.c.) ain10 (n.c.) ain9 ain1 (n.c.) ain8 ain0 ain2 ain3 pin configurations max11613 top view (bumps on bottom) a b c wlp 1234 ain0 ain1 ain2 ain3/ ref gnd gnd gnd gnd v dd gnd sda scl + package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 ?ax u8cn+1 21-0036 90-0092 12 wlp w121c2+1 21-00 09 refer to application note 1891 16 qsop e16+1 21-0055 90-0167
max11612?ax11617 low-power, 4-/8-/12-channel, i 2 c, 12-bit adcs in ultra-small packages maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/09 introduction of the max11612/max11613 1 7/09 introduction of the max11614?ax11617 1 2 3/10 changed absolute maximum ratings and timing diagram 2, 12 3 2/11 added wlp to ordering information , absolute maximum ratings , electrical characteristics, pin description , and package information 1?, 8, 21

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